TM 11-6625-444-14-2
input (U405 pin 6), the high gain output will
swing towards the positive supply (+5 V). This
causes a logic "high" to be present at NAND
The reference input (inverting) to U404A pin 1
gate U403D pin 8 and because 4 (figure FO-5)
i s set to produce - 1 9 5 , 0 0 0 counts (approx.
is "high" (Autorange), the output of this gate (pin
-9.75 volts) by adjusting R405. If a voltage >
10) is "low". This turns off the photo-cell U407
-9.75 volts (i.e. -9.80 volts) is applied to the
and causes a logic "high" to be present at U50
non-inverting input (U404A pin 2), the high gain
pin 9; producing a "Down Range command".
( > 10,000) operational amplifier will swing
quickly to the negative supply voltage (-15 V).
This will turn off the photo-cell in U406 and
If the output signal voltage is > -0.6 V (i.e.
cause pin 5 to go high (+5 V). The result is a
-0.7 to -9.75 volts), then the output of U405B
logic "high" at U50 pin 5; producing an "Up
will swing to nearly the minus supply voltage
Range command".
(-15 V) and cause a logic "low" to be at U50 pin
9. This tells the autorange circuits to remain at
the present range.
If the output signal voltage is < -9.75 volts
(i.e. -9.70 volts), then the open collector output
o f U404A goes towards the positive (+5 V)
supply, causing the photo-cell in U406 to con-
duct. This results in a logic "low" at pin 5 of
A reference voltage representing + 12,000
U406 and thus; a logic "low" at U50 pin 5. This
counts is applied to the non-inverting input of
causes the autorange circuits to stay (or hold) at
U405A pin 2 and is set to approx. +0.6 volts by
the present range.
adjusting R407. If a voltage < 0.6 volts (<
12,000 counts) is applied to the inverting input
(U405A pin 1), the output will swing towards the
open collector supply voltage of +5 V. This re-
sults in a "low" from U403D pin 10, turning off
The reference input (non-inverting) to U404B
the U407 photo-cell and causing a logic "high"
pin 6 is set to produce +195,000 counts (approx.
to be present at U50 pin 9. This produces a
+9.75 volts) by adjusting R406. If a voltage >
"Down Range command".
+9.75 volts (i.e. +9.80 volts) is applied to the
inverting input (U404B pin 7), the high gain am-
plifier will swing to approx. the negative supply
If the signal voltage is > +0.6 V (i.e. +0.7 to
voltage (-15 V). This again results in a logic
+9.75 volts), then the output of U405A will swing
"high" at U50 pin 5 producing an "Up Range
to the minus supply voltage (-15 V). This results
command".
in a logic "low" at U50 pin 9 causing the auto-
range circuits to remain at the present range.
If the output signal voltage is c +9.75 volts
(i.e. +9.70 volts), then again a logic "low" will be
presented to U50 pin 5. This causes the auto-
Refer to figures FO-8 & FO-11
range circuits to stay (or hold) at the present
range.
Up Range Command: On any range except
the 1000 V range, a logic "high" is present at
U50B pin 6 enabling the NAND gate. When a
"high" (Up Range command) is applied to U50B
A reference voltage representing -12,000
pin 5, a logic "low" is at the output (pin 4). This
counts is applied to the inverting input of U405B
"low" is directed to pin 5 of U51, the BCD
pin 7 and is set to approx. -0.6 volts by adjust-
Up/Down (U/D) Counter, enabling it. The "high"
ing R408. If the voltage is < 0.6 volts ( <
(Up Range command) is also steered to U51 pir
12,000 counts) is applied to the non-inverting
10; selecting the up-count mode, see table 5-7
