c. Switches Q22 through Q26 are the main
elements of the anode strobing control circuit.
They are turned on sequentially by shift register
signals A through E, beginning with signal A.
turned on only during the second half of each
of these switches controls switches Q27 throught
Q31, which apply +200 volts dc to the anode of
each readout tube.
d. Overrange indicator V2 is operated by
transistors Q17 and Q18. These transistors are
controlled by the 6-state cycle control shift
register, the 16-state binary counter, and the
range counter. The zero character in this tube is
illuminated only when the range counter com-
mands the 1 range, and when the count in the
binary counter is less than 10. The one character
is illuminated when the count in the binary
counter is 10 or 11. Decoder driver U4 is a
monolithic BCD to decimal decoder which accepts
the 4-bit BCD output of the 16-state binary
counter, decodes each digital word, and selects
one of ten output drivers. The cathodes of readout
tubes V3 through V7 are connected in parallel.
SCO functions only when the SAMPLE RATE
These 10 nodes are, in turn, connected to the 10
control is switched to the EXT position and
available outputs of the decoder driver.
samples are initiated through the external trigger
consists of programmable unijunction transistor
input of the data output unit (DOU) option. In
this circumstance, the emitter of Q6 is normally
high. Thus, the gate of PUT Q8 is near the supply
in its normal operating state. Resistors
voltage and the PUT is disabled. A trigger from
R12 and R14 provide a bias level for the gate of
the DOU, however, pulls the emitter of Q6 to
the PUT. When capacitor C3 charges to ap-
ground. Its collector follows, causing the gate of
proxmiately 0.6 volt above the gate bias level, the
PUT turns on and discharges C3 through R15.
Q8 to be more than 0.6 volt below the anode and
the PUT fires once. If the corresponding sample
This action generates an output pulse which
results in a range change, the range delay one
commands the measure/storage cycle J-K flip-
flop U3A to the measure period to take a sample,
Signal No. 3 and CR7. This means that no
samples may be commanded until the range delay
clocked input to the flip-flop. If the sample results
one-shot times out. At the end of this time delay,
in a command to autorange, signal 3 from the
the SCO is automatically retriggered through
range delay (A2) one-shot turns off Q6 and
CR8 by Signal No. 2 from the range delay one-
disables the SCO to allow time for analog signal
shot. Diode CR9 and resistor R10 insure that
conditions to settle on the new range before
capacitor C3 is charged rapidly to ready the PUT
another sample is taken. Capacitor C3 begins to
for the next trigger pulse. Signal No. 8 interrupts
recharge and the SCO cycle begins again. The
the cycle control shift register on the logic board
(A8) by forcing it directly to the E subperiod.
constant of R and C3, and the gate bias level. The
This is done to minimize the time between the
sample command (trigger) and actual sample.
through the front panel SAM PLE RATE control.
g. The measure/storage cycle circuit is
Transistor Q7 and its base bias network (R11 and
composed of J-K flip-flop U3A. The clocked input
R13) insure that PUT Q8 is turned off by forcing
of U3A is connected to ZERO through a bias and
the gate and anode to the same potential after C3
differentiating network composed of capacitor C4