TM 11-6625-444-14-1
line. Gate U2A prevents autoranging below the
the next lower range. In either case, the first
output pulse triggers the range delay one-shot to
range in the VDC function, while gate U2B
prevents autoranging below the 1 range in any
allow the analog signal conditioners to settle in
function. Gate U3B is the master up-range
the new range.
control. It enables the range oscillator only if an
f. Transistors Q1, Q2, and associated com-
up-range is to be expected.
ponents make up the range delay one-shot
multivibrator. A range change pulse from the
the range-up enable line, provide one input for up-
range oscillator applied to the base of transistor
range control gate U3B. The result is that U3B is
Q2 turns this transistor on and transistor Q1 off,
enabled for 1.5 milliseconds (the second half of the
thereby placing the one-shot multivibrator into
A subperiod of a measurement period) if an up-
its unstable state. The RC charge time of com-
range is to be executed. Signals applied to diodes
bined capacitors C2, C6, and resistor R5, and the
CM through CR8 and CR10, coupled with the
current through R16 determine how long the one-
range-down enable line provide a negative going
shot remains in its unstable state. With the filter
signal to the range oscillator at the end of the A
selected, no current flows through R16 and the
subperiod of a measurement period if a down-
timeout is about 220 milliseconds. Without the
range is to be executed. Thus, there are two ways
filter selected, the timeout is decreased to about
25 milliseconds because some current flows
which can enable the range oscillator.
through R16. Signal No. 3 disables the sample
d. The range oscillator is composed of
capacitor C4, resistors R14, and programmable
command oscillator during the range delay item.
Signal No. 2 retriggers the SCO at the end of the
unijunction transistor (PUT) Q4, with the output
range delay time.
of this oscillator appearing at the cathode of PUT
Q4. The PUT is fired, discharging capacitor C4
g. Transistor Q5 and associated components is
a circuit that prevents the instrument remaining
through resistor R15, when the gate is about
in a disallowed range, as in 10,000 VDC, when
-0.6 volt relative of the anode. Thus the PUT
turned on. When Q5 is turned on by the inputs of
is fired to produce one output pulse by lowering
gate voltage or by raising the anode voltage, such
on the set line of the counter and thereby forces
that the voltage difference between these ele-
the instrument out of the 10,000 range.
ments is as indicated above. The firing of PUT Q4
discharges capacitor C4 and reduces the anode
5-10. Power Supply.
and gate voltages. This action causes Q3 to turn
on and force the anode and gate of Q4 to the same
potential. Transistor Q4 turns off and capacitor
a. Power s u p p l y ( A 1 ) c o n s i s t s o f f o u r
C4 charges through R14. If the firing potential
regulators: a + and - 18 volts regulator; a 200
between the gate and anode of Q4 is established,
volts regulator; a 5 volts regulator. The power
Q4 again fires and the cycle is repeated to produce
supply furnishes all required operating power.
t h e second output pulse. The frequency of
b. The +18- and -18-volt regulators obtain
oscillations is set by the level of gate voltage
filtered dc voltage from the full-wave rectifiers
applied and the charging time constant of R14
consisting of diodes CR5 through CR8 and filter
and capacitor C4.
capacitors C2 and C5. The +18 volts regulator
e. Control of the gate of PUT Q4 is effected by
consists of operational amplifier U1 and series
one of two mutually exclusive inputs. One of
pass transistor Q3. The voltage reference for the
these ia associated with ranging up and is
+18 volts regulator is derived from reference
identified on the A2 schematic diagram as the
amplifier U9 and temperature compensation
output of gate U3B. The other of the two inputs is
trasistor Q23 on the logic board (A8). The -18
associated with ranging down and is identified as
volts regulator consists of operational amplifier
the range. down enable line. In an up-range
U2 and series pass transistor Q5. The -18 volts
regulator is referenced to the +18 volts.
situation, the output of U3B pulls low for 1.5
c. The +200 volts regulator is operated from a
m i l l i s e c o n d s during which time the range
oscillator outputs five pulses. In a down-range
full- wave bridge rectifier and filter consisting of
situation, the range-down enable line pulls low.
diodes CR1 through CR4 and capacitor C1. The
reference for the +200 volts regulator is the +18
This signal is capacitively coupled through C3 to
volts. Voltage variations are amplified in tran-
the gate of PUT Q4 causing it to output one
sistor Q2 and applied to series pass transistor Q1.
pulse. Five pulses counted by the range counter
d. The +5 volts regulator is operated from a
(A14) command a transition to the next higher
full-wave rectifier and filter consisting of CR10
range, while one pulse commands a transition to
5-15
