TM 11-6625-444-14-1
and resistors R18, R19. When the M output of
of the instrument for a given range. However,
U3A is high, the voltmeter is in the measurement
even though turned on, transistor Q3 is inef-
period of the measurement/storage cycle. When
fective in gating the PUT unless an enabling
prevails. The clocked input is normally high as
determined by the bias network, and because this
NAND gate U2A located on the logic board (A8).
is a master-slave type flip-flop, the master is
Signal No. 7 is the UP range signal that is applied
connected directly to the J and K inputs and
to NAND gate U3B on the range delay board
isolated from the outputs. If the SCO outputs a
(A2). It is generated at the emitter of transistor
pulse, the J input goes high and causes the
Q37 when this transistor is turned on by the PUT
master to assume the true state. At the start of
firing. After firing, the PUT is reset by the ap-
the next ZERO (0) time, the clock pulses low
plication of the positive-going edge of the M
causing the slave, and, hence, the outputs, to
signal applied to its cathode through C1.
assume the state of the master. That is to say, the
i. The range counter circuit is composed of J-K
output goes true and initiates a measure cycle. At
flip-flops U2A and U2B. The clocked input to the
the same time, the master is updated as a func-
range counter is provided by J-K range flip-flop
tion of the new J and K inputs. Thus, at the start
U3B, that has as its clocked input signal No. 6.
This signal originates in the range oscillator on
of the next ZERO (0) time, the slave assumes the
false state existing in the master, and the storage
the range delay board (A2) and is pulsed high
period is initiated. Not until the SCO pulses again
everytime the range oscillator PUT fires. The J-K
will another measurement period be initiated. The
inputs to the range flip-flop U3B are tied together
idealized
at the output of the measure/storage cycle J-K
o u t p u t o f the
mea-
sure/storage cycle J-K flip-flop is seen by viewing
flip-flop U3A and go high every measurement
waveform No. 8 and its two input generating
period. The range counter is a divide-by-6 counter
waveforms 6 and 7 in figure 5-5 .
that provides the six possible binary states for
range counting, five pulses being considered an
h. The overrange driver circuit is composed of
up-range command and one pulse being con-
programmable unijunction transistor (PUT) Q4,
sidered a down-range command. Signal No. 6
transistors Q3, Q5, and Q37, and associated
applied to the clocked input of range flip-flop U3B
alters the six states of the range counter.
R2 and R4 are not part of the driver circuit but
Transistor Q35 is provided to pull the range
constitute a delay line in the speed at which the
counter out of an unallowed state that may occur
range delay one-shot multivibrator circuit on the
at turn-on.
range delay board (A2) times out. The time-out
5-9. Range Delay
delay is a function of the FILT button being
depressed on the front panel, applying a low at
a. Range delay circuit (A2) consists of a series
the base of PNP transistor Q2, turning it on, and
of gates, a range delay one-shot multivibrator,
effectively holding transistor Q1 in the range
and a range oscillator. The gates allow the
delay one-shot off (time-out status) for a longer
specified set of ranges to be attained, which is
time than would otherwise occur if transistor Q2
dependent upon the function called on the front
were not turned on by the filtering function being
panel. The range oscillator generates pulses which
activated. The overrange driver PUT Q4 is turned
trigger
the
range delay
on when its gate voltage is depressed about 0.6
one-shot
while
simultaneously causing the range counter (A 14)
volt relative to the anode voltage. The differential
to change states. The range delay one-shot
voltage developed across resistor R64 (tied
prevents further ranging for a specified time to
between the gate and anode of the PUT) when the
allow the analog signal conditioners to settle in
PUT conducts turns on PNP transistor Q5, and
the new range.
resultingly, turns on the OVER lamp in the
b. The gates are U2A, U2B, U2C, U3A, and
function display annunciator. The gate to anode
U3B. Gates U2C and U3A are up-range stops
voltage relationship that turns on transistor Q5
which pull down on the range-up enable line. Gate
and the OVER lamp is brought about by NPN
U2C stops the internal ranging from going above
transistor Q3 when it is turned on. Transistor Q3
a 10,000 range while gate U3A prevents
is turned on by the twelth output pulse from the
autoranging above the 1,000 range on the VDC
CCO being applied to its base. Twelve output
function. Gates U2A and U2B are down range
pulses from the CCO indicate greater than 20
stops which pull down on the range-down enable
percent overvoltage is being applied at the input
5-14
