TM 11-6625-444-14-1
S e c t i o n Il. CIRCUIT DESCRIPTION
a. The buffer (A 11) provides a full-scale dc
5-4 Introduction
voltage of 10V DC. It consists of three basic
This section contains detailed circuit description.
elements: input voltage divider, amplifiers, and
Each major circuit assembly or group is described
control logic. In the 100 and 1,000 volts range
separately. All discussions are keyed to the
input attenuation occurs, while in the 10 volts
schematic diagrams located at the rear of the
range the input is processed without attenuation
manual (fig. FO-2 through FO-11).
or amplification. This mode of operation is
5-5. Buffer
depicted in block diagram form in figure 5-2.
voltage to the base of differential amplifier Q5B
b. The input to the buffer is derived from the
that results in a buffer output voltage equal to
HI and LO input jacks (J25 and J26) which are
zero when the input voltage is zero. This last
shown on the interconnect and wiring diagrams
potentiometer is labeled DC ZERO on the front
(fig. FO-10 and FO-11). Buffer input current
panel.
limiting resistors 1R1 and 1R2 are also located on
the system diagram, along with the high and low
e. Overload protection for dual differential
amplifier Q5 is afforded by the combination of
inputs to the buffer, at jacks J4TM and JITR,
components R2, CR1, Q11, and current limiting
respectively, of terminal block No. 1.
resistors R1 and R2 shown on the system wiring
c. In the high volts mode of operation, the
diagram Positive overvoltage protection is af-
buffer amplifier receives the input voltage directly
forded by transistor Q11 which clamps amplifier
(10V range) or receives a scaled down voltage
o u t p u t to 1.7 volts. Negative overvoltage
through an input voltage divider consisting of R5
protection is afforded by diode CR1 which clamps
through R10. The buffer is a unity gain inverter;
the input to -1.7 volts. The current drawn
therefore, its output is the inverse of the received
during an overload is limited by the total input
input. For example, an input of +1000V would be
resistance of 147k ohms.
scaled down to +10V through the input divider.
With +10V as its input, the buffer output is
f. Compensation circuits are provided to
-10V.
reduce the temperature coefficients of the input
offset voltage and offset current. Transistor Q2
present that would cause buffer output with no
and surrounding circuitry provides through R18
input is compensated by use of two poten-
and R19 the temperature varying base current
required by input transistor Q5. Transistor Q3
tiometers: COARSE DC ZERO, which balances
the base emitter voltages of the input differential
compensates the temperature variation of the
amplifier 05 by adjusting the collector current
base-emitter voltage in dual transistor Q4 to
ratio, and the second potentiometer, DC ZERO,
insure that input transistor Q5 remains at sub-
which affords a fine adjustment via the front
stantially the same bias conditions regardless of
panel by applying just that amount of nulling
temperature.
