TM 11-6625-444-14-1
FUNCTIONING
OF
EQUIPMENT
Section I. BLOCK DIAGRAM ANALYSIS
5-1. Introduction
the A/D converter. Internal reference voltage for
the dc measurement mode is produced by the
This section briefly describes major circuit
reference voltage supply. Function of the CCO
functions of the voltmeter. First, the dc voltage
and four-bit counter are described under the A/D
measurement mode is discussed followed by a
converter.
description of the ratio mode. Both discussions
e. A/D Converter. The A/D converter (A9)
are keyed to the block diagram shown in figure 5-
receives the output of the active filter, determines
the polarity, and serially digitizes the input
5-2. Dc Measurement Mode
voltage. The digitizing process is controlled by
a. General. The voltmeter measures and
commands from the logic assembly. Circuitry
d i s p l a y s (digitally) dc voltages from 0 to
consists of an inverting amplifier, polarity
1100V. Circuitry consists of an input buffer,
detector, sample and hold, A/D amplifier, ladder
active filter, logic circuitry, an analog-to-digital
switches, and an analog comparator.
(A/D) converter, digital display, range delay,
(1) The inverting amplifier receives the
switching circuitry, and a power supply. Circuit
positive or negative input. It inverts any positive
interface is shown in figure 5-1.
input such that its output applied to the A/D
b. Buffer. The buffer (A 11) receives the dc
amplifier is always negative. Polarity of this
input voltage and scales it up or down so that a
signal is sensed by the polarity detector the
fullscale input produces a 10V output to the
output of which is applied to the display section.
following active filter. Selection of the lV range
Any output voltage from the A/D amplifier
sets the buffer gain to 10, thus providing a 10V
greater than V REF produces an output from the
output for 1V input. Gain is fixed at unity in the
analog comparator, which enables the CCO in the
10V, 100V, and 1,000V ranges and the input is
logic assembly to send output pulses to the binary
scaled down using an input divider. A process in
counter. The binary counter output gates ap-
the buffer yields a negative output for a positive
propriate ladder switches to produce a voltage
input. The opposite is true for a negative input,
across the ladder resistors. This voltage is equal
which yields a positive output.
in value, but opposite in polarity, to that portion
c. Active Filter. The active filter (A10) sup-
of the A/D amplifier input originally applied. As
presses ac noise present in the buffer output. It
the degenerate affect of the ladder voltage causes
consists of a voltage follower and a four-pole
the A/D amplifier output to fall below V REF
filter. Filtering is in effect when the FILTER
the analog comparator will no longer enable the
s w i t c h is depressed. When filtering is not
CCO. At this point, the digitizing process for the
selected, the four-pole filter is bypassed and the
most significant digit is complete.
circuit functions as a voltage follower. The
(2) The remaining voltage level at the output
resulting output is applied to the A/D converter.
of the A/D amplifier (voltmeter input minus the
d. Logic. The logic (A8) produces the master
most significant digit) is then stored in the
timing signals from which measurement periods
sample and hold circuit until the next logic gate
in the voltmeter are derived. It also produces the
enables its application to the A/D amplifier. Each
master reference voltage upon which the volt-
decade of this recirculated remainder is then
meter accuracy and stability is based. The cir-
digitized in a similar fashion with one exception:
cuitry consists of a master clock, a six-state shift
The recirculated remainder voltage (now the A/D
register, a current controlled oscillator (CCO), a
amplifier input voltage) and the ladder voltage
four-bit counter, and a +7V DC reference voltage
are now the same polarity.
supply. Gating signals which synchronize all
timing circuitry are produced by the master clock.
f. Display. The display (A14) decodes the
binary counter output and digitally displays the
The shift register is driven by the master clock
input voltage magnitude and polarity. It also
signal and produces digit cycle control signals for
