TM 11-6625-2616-14
schematic diagram.
(2) Pins 1 and 2 are triggered by the stor-
quency counter counts 120,000 counts prior to
age display pulse (end of reading).
the storage display pulse which occurs at the
end of a reading. A down-signal is generated
(3) Pin 4 is on through the auto-range
similarly when the counter counts 10,000 or less
switch, S2.
pulses before the storage display pulse occurs.
(4) Pin 3 is on from the bidirectional count-
er, U1 (on the signal conditioning board).
c. To generate a down-pulse at U5, pin 8, the
Description
following conditions must occur:
a. U1 (pins 1, 2, and 3) detects the presence
(1) Pin 10 must be on through the auto-
of 120,000 counts and drives buffer U2 (pins 4,
range switch, S2.
5, and 6). Pin 6 drives the following circuits.
(2) Pins 12 and 13 must be pulsed by the
(1) Q13 which lights the overload lamp.
storage display pulse.
(2) Q22 which shuts off the clock oscillator.
(3) Pin 9 must be held on by flip-flop Ul,
(3) Pin 5 of U5.
pin 11 when the above occurs.
(4) Pin 11 is held on by bidirectional count-
b. U5 will produce an up-range signal at pin
er, U1.
6, when.--
(1) Pin 5 is turned on by a count of 120,000.
d. Flip-flop U1 is set by U4, pin 11, at the
