have a very low leakage on the ICES in-circuit test.
These devices, however, will either be rejected by
Insulated gate field effect transistors,
the beta test, or they will show up as having
denoted by the letter (I) before the chan-
abnormally low resistive loadings.
nel designation, are prone, to destruction
through accumulation of static charge
f. The last column in section II of this appendix
on the gate. Permanent damage may
gives a drawing number for each transistor. Refer
result if the gate voltage rating is ex-
to this drawing in section V of this appendix when
ceeded for an extremely short time pe-
connecting the test leads to the transistor under
riod. All personnel and equipment, in-
grounded when working with this type
D-3. Field Effect Transistor (FET) Data
of device. When testing insulated gate
a. Section III of this appendix presents data on
field effect transistors, use POLARITY
field effect transistors. One of the most important
switch setting reversed from the above
parameters of field effect transistors is transcon-
procedure for ordinary FET.
ductance. The transconductance (GM) is presented
in micromhos (mhos).
D-4. Diodes and Rectifiers
b. Field effect transistors are measured for trans-
Section IV of this appendix presents data on
limited 10 mA current source. This choice of bias
diodes and rectifiers. To provide maximum infor-
conditions insures that the TS1836D/U will not
mation, all JEDEC registered diodes and rectifiers
damage the device under test but, at the same
have been listed; however, some of the devices
time, will cause the observed GM to differ from
listed, such as silicon-controlled rectifiers, micro-
the amount by which IDSS exceeds 10 mA. The
have reverse leakage as a specified parameter.
transconductance data in this appendix has been
These devices are marked with a letter (a).
adjusted to reflect these test conditions. When no
transconductance value is listed, the manufac-
turer does not specify a transconductance and
D-5. Transistor Basing Data
a qualitative test only should be made.
Section V of this appendix presents the transistor
basing data. When connecting the test leads on
When testing N-channel field effect tran-
the test set to a transistor or other device under
sistors, use the NPN position on the
test, consult the proper drawing number to iden-
POLARITY switch. For P-channel de-
tify the emitter, base, and collector leads or other
vices, use PNP.
terminals of the device.